With the advent of less expensive semiconductor memory, modern computer and microcomputer systems have been able to use bit-mapped video displays for the output of data from the system. As is well known, a bit-mapped display requires a memory which can store at least one binary digit (bit) of information for each picture element (pixel) of the display device. Additional bits stored for each pixel provide the capability of the system to render complex images on the video display, such as multi-color images, and background and foreground images, such as a graphics background with textual information overlaid thereupon. The use of bit-mapped storage also allows for data processing operations to easily generate and modify the stored image.
Modern video display devices are often of the raster-scan type, where an electron gun traces horizontal lines across the display screen in order to generate the displayed pattern. In order for a displayed raster scan image to continue to be displayed on the video screen, the image must be refreshed at periodic intervals. A common refresh rate for the cathode ray tube video display devices is 1/60 of a second, since the refresh operation carried out at that speed is not noticable to the human user of the system. However, as the number of pixels displayed on a screen increases, in order to increase the resolution of the displayed image, more and more bits of information must be accessed from the bit-mapped memory in the refresh interval. If the bit-mapped memory has but a single input and output port, the percentage of time during which the data processing unit can access the bit-mapped memory decreases with the pixel size of the display if the refresh interval remains constant. In addition, the speed of the memory must increase, since more bits must be output during a fixed period of time.
Multiport random access memories have been developed which provide for high-speed output of data to the video display and also for increased accessability of the memory contents to the data processing device. The multiport memories accomplish this by having a first port for random access and update of the memory by the data processing unit of the computer system and a second port for serial output of the memory contents to the video display independent from and asynchronous with the first port, thereby allowing access to the memory contents during output of data to the video display terminal. Examples of multiport random access memories are described in U.S. Pat. No. 4,562,435 (issued Dec. 31, 1985), U.S. Pat. No. 4,639,890 (issued Jan. 27, 1987), and U.S. Pat. No. 4,636,986 (issued Jan. 13, 1987), all assigned to Texas Instruments Incorporated.
The multiport random access memory described in said U.S. Pat. No. 4,636,986 has four random access input/output terminals, and four serial access input/output terminals, so that the single memory device appears to have four memory arrays. This allows a single random access to read or write four data bits simultaneously, with a single address value, and also allows a by-four serial output for purposes of data communication to the video display. An external parallel-to-serial register can then receive the four serial output bits, and shift them to the video display at the display refresh rate; this allows the memory register to shift at one-fourth the rate of the video display, reducing the speed requirements of the semiconductor memory.
Other uses of the by-four organization provide for enhanced image display capabilities. For example, the by-four organization is useful in multi-color displays, since the four bits associated with each address can be associated with a common display picture element ("pixel"). This configuration provides for the storage of a a binary code representative of up to sixteen colors for each corresponding pixel of the video display. Another use of the four bits is to use one of the bits for representing text, and the other three bits for representing an eight bit color code for a graphical background; the by-four memory thus facilitates the overlaying of a text message on a graphics image.
In such applications, where the image information is stored by multi-bit color codes in a bit-mapped system, often a large number of memory addresses, or pixel locations, contain the identical color code information. Such is the case where a large portion of the image is filled with a given color. In prior dual-port memory devices, such as those in the above-referenced U.S. Patents, the operation required to perform such a "fill" would be repeated write operations to the necessary number of memory locations, applying the same input data for each write cycle. In addition, the representation of data points in such a filled image often results in the same co)or data being stored in a multiple of memory locations in close proximity to one another.
It is therefore an object of this invention to provide a dual-port memory device having an on-chip data register, for the storage of a data pattern which may be written into a number of memory locations without requiring the application of input data to the data pins of the memory.
It is another object to provide such a dual-port memory with such an on-chip data register which can either select the data in the data register or data at its input terminals to be written to the selected memory location on a cycle-by-cycle basis.
It is another object of this invention to provide such a dual-port memory to which the contents of the data register may be written to a number of adjacent memory locations during the same write cycle.
It is therefore yet another object of this invention to provide such a dual-port memory where certain bits of the data register may be inhibited from being written during a given write cycle.
Other objects and advantages of the instant invention will become apparent to those of ordinary skill in the art having reference to the following specification, in combination with the drawings.